Altera Job Posting: System Level Debug Design Engineering, MTS

Hi Eveyone.

I wanted to make you aware of an open req for a position related to embedded systems. The (new) description is below. The title and description will be updated on Altera.com to the one below early next week. If you are interested and feel that you qualify, please apply to Requisition ID 443 on altera.com

http://tbe.taleo.net/na3/ats/careers/requisition.jsp;jsessionid=70f26d85104409d8be764ae9b8ae86bd.na3_primary_jvm?org=altera&cws=1&rid=443

Regards,

-Joel-

requisition id 443

system level debug design engineer, mts

As a System-Level- Debug Engineer you will be a part of the team specifying and implementing Altera's system level debug solutions including tools and methodology for:

- Processor Debug and trace

- Statistics gathering and visualization

- HW/SW Co-simulation

- Hardware / Software in the loop

As an System Level Debug Expert at Altera you will design and develop the tools that system designers use to debug the hardware and software and interactions between the two in an FPGA system. This will span from low-level signal debugging up to architectural and performance modeling of throughput in a system. You will also have close collaboration with other groups in applications, marketing, and sales to understand unique customer requirements and implement these in a set of world-class system level debug tools.

Requirements: BS Electrical Engineering, Computer Science or equivalent. 5+ years experience developing and debugging embedded systems or developing debug tools for embedded systems. Strong and clear communication skills. Strong C++, Java, or HDL language experience. Demonstrated success in working at multiple abstraction levels – you must be smart and get things done. Prior experience using Altera's products (FPGAs, IP, Nios, Quartus, or System Console) a plus.