Altera FPGA Fabric Timings - Avaliable?

At that level, it can come down to understanding the fundamental technology. FPGAs use 4/5/6 input LUTs. Knowing this, then you should be able to work out (or at least look at the mapping diagram) how many layers of LUTs there are in your logic. If you have 2 layers, then 1 extra register is all you need, as this is all thats needed to break up the logic. any more wouldnt be beneficial.

What I will say is that many timing problems dont come in the LUT logic, they are a consequence of DSPs and RAMs being in fixed locations. It is quite expensive, timing wise, to route into/out of these. If timing is getting tight you can start failing timing at the block boundaries, likely because the fitter is being forced to pull a single register in two directions to meet timing. Adding extra registers here can be very beneficial, as it gives the fitter more options to place/move registers.