--- Quote Start ---
If your design fails timing, then the best course of action is to increase the number of pipeline stages and reduce the number of levels of logic (sequential luts) between registers. This is most easily done in the RTL.
--- Quote End ---
Which is exactly what I'm trying to do, but I just thought there might be a way to do it by checking timings rather than just trial and error, "suck it and see" type methods.
For instance, if I need to restructure a 32-to-1 LUT to make it quicker, I figured it would be nice to know if I should do it in two or three registered stages based on some maximum delays and calculations.
But I'll give it a go and see what it routes.
Honored Contributor
