Altera FPGA Fabric Timings - Avaliable?

You usually wouldnt generate the logic yourself. Your RTL code will be converted by the synth tool. Hand placing LUTs and registers is a slow and laborious process, and you are unlikely to get better results than the synthesis and place and fitter. These can use your timing specs to help them get good results.

The timing analysis has worst case timing for all routing and LUTs, with several models (standard being fast/slow and high temp and low temp). It works out the delay between registers and if it meets the timing specs (usually specified with a clock definition) then it will work in the chip.

If your design fails timing, then the best course of action is to increase the number of pipeline stages and reduce the number of levels of logic (sequential luts) between registers. This is most easily done in the RTL.