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The technology is fundamentally different. Altera uses luts to model logic. As such, the lut delay is very small compared to the routing. The luts also do not implement a single gate, but anything from one to several.
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We'll sure, but if I want to chain two LE's 4-to-1 LUTs together to form a larger LUT, surely I can bypass one LE's register if I know how long it will take to travel through one LUT to the input of the next LUT, and allow for it by leaving enough time between clocks.
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For FPGAs, you should have a fully synchronous design, which can then be timing analysed, so timing simulation not necessary. As long as rtl simulation is verified and running analysis passs, your design should work in FPGA.
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But how can timing analysis take place without knowing the parameters?
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