Altera FPGA Fabric Timings - Avaliable?

The technology is fundamentally different. Altera uses luts to model logic. As such, the lut delay is very small compared to the routing. The luts also do not implement a single gate, but anything from one to several.

The routing is affected by Pvt, process voltage temperature, so accurate timing cannot be given in the datasheet. In addition, the routing will likely change from build to build.

For FPGAs, you should have a fully synchronous design, which can then be timing analysed, so timing simulation not necessary. As long as rtl simulation is verified and running analysis passs, your design should work in FPGA.