Solved
Forum Discussion
ZAhma1
New Contributor
6 years agoHi Anand,
As you may be aware with most FPGA IPs, there is no data valid signal. You just have to wait the suggested number of cycles and hope the output is correct.
I've created a sample project with the IP in question and also added a testbench which will run the problem cases. I'll attach them here.
ZAhma1
New Contributor
6 years agoAnd here is the testbench