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AnandRaj_S_Intel
Regular Contributor
6 years agoHi Ahmad,
You have to check the output of ALTERA_FP_FUNCTION when valid signal is high.
you can check with example design from user guide
Please share you design or image.
Regards
Anand
- ZAhma16 years ago
New Contributor
Hi Anand,
As you may be aware with most FPGA IPs, there is no data valid signal. You just have to wait the suggested number of cycles and hope the output is correct.
I've created a sample project with the IP in question and also added a testbench which will run the problem cases. I'll attach them here.
- ZAhma16 years ago
New Contributor
And here is the testbench