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Altera_Forum
Honored Contributor
17 years agoAltera Debug Client Issue
Im a new to FPGA and learning through Altera's tutorials. In one of them i need to create a Nios II processor and then, create an application file through the Altera Debug Client. when i try ...
Altera_Forum
Honored Contributor
17 years agoGo to your project folder, and find the build log of your nios II system
(example: my SOPC builder built a softcore processor with the name nios_system, along with it a log file is also created) LOG FILE below:(nios_system.log) Altera SOPC Builder Version 7.20 Build 203 Copyright (c) 1999-2007 Altera Corporation. All rights reserved. # 2009.02.01 16:50:05 (*) mk_custom_sdk starting # 2009.02.01 16:50:05 (*) Reading project C:/lab_4/nios_system.ptf. # 2009.02.01 16:50:06 (*) Finding all CPUs # 2009.02.01 16:50:06 (*) Finding all available components # 2009.02.01 16:50:06 (*) Reading C:/lab_4/.sopc_builder/install.ptf # 2009.02.01 16:50:06 (*) Found 80 components # 2009.02.01 16:50:09 (*) Finding all peripherals # 2009.02.01 16:50:09 (*) Finding software components # 2009.02.01 16:50:09 (*) (Legacy SDK Generation Skipped) # 2009.02.01 16:50:09 (*) (All TCL Script Generation Skipped) # 2009.02.01 16:50:09 (*) (No Libraries Built) # 2009.02.01 16:50:09 (*) (Contents Generation Skipped) # 2009.02.01 16:50:09 (*) mk_custom_sdk finishing # 2009.02.01 16:50:09 (*) Starting generation for system: nios_system. . . . . # 2009.02.01 16:50:13 (*) Running Generator Program for cpu # 2009.02.01 16:50:19 (*) Checking for plaintext license. # 2009.02.01 16:50:21 (*) Plaintext license not found. **** this is what counts************* check it up and let me know # 2009.02.01 16:50:21 (*) Checking for encrypted license (non-evaluation). # 2009.02.01 16:50:22 (*) Encrypted license found. SOF will not be time-limited. # 2009.02.01 16:50:38 (*) Creating encrypted HDL # 2009.02.01 16:50:42 (*) Running Generator Program for onchip_mem # 2009.02.01 16:50:45 (*) Running Generator Program for jtag_uart # 2009.02.01 16:50:48 (*) Running Generator Program for timer # 2009.02.01 16:50:50 (*) Making arbitration and system (top) modules. # 2009.02.01 16:50:58 (*) Generating Quartus symbol for top level: nios_system # 2009.02.01 16:50:58 (*) Generating Symbol C:/lab_4/nios_system.bsf # 2009.02.01 16:50:58 (*) Creating command-line system-generation script: C:/lab_4/nios_system_generation_script # 2009.02.01 16:50:59 (*) Running setup for HDL simulator: modelsim # 2009.02.01 16:50:59 (*) Setting up Quartus with nios_system_setup_quartus.tcl c:/altera/72/quartus/bin/quartus_sh -t nios_system_setup_quartus.tcl