Honored Contributor
Honored ContributorI strongly recommend you use external buffers/drivers to drive such a signal. Sourcing 35mA from an I/O pin might work for a bit but, I'm very sure, it'll soon fail.
The drive strength available is dependant on the I/O standard you select. Refer to the "I/O Standard Specifications" in the cyclone iv device datasheet (http://www.altera.com/literature/hb/cyclone-iv/cyiv-53001.pdf), page 1-12. To drive 35mA I suspect you're hoping to use one of the higher I/O voltages (perhaps 3.3V) for which you won't be able to select 16mA drive strength (through the Pin Planner). You can at 2.5V. I agree with Anakha, ganging up pins can be considered. Ensure you switch them on the same clock edge and I doubt you'll run into any issues. However, although I can't find the detail at present, I'm very sure there is a limit as to how much current you can drive out of a bank of pins. Don't expect to create lots of groups all driving high currents. Your FPGA won't last as long as, I'm sure, you'd like it to. Regards, Alex
