ALT2GXB reset sequence without RX Clock

I have concluded that there is no way to get the ALT2GXB reset sequence working without having a valid RX PLL clock available when the gxb_powerdown signal deasserts. I have therefore configured the CRU to use the Arria GX Dev Kit board's 100 MHz clock as both source for the TX PLL as well as for RX PLL input. I figure that the CRU will first lock to the local 100 MHZ PLL and then switch over to lock to the embedded clock in the PCI Express data once available. The attached JPG seems to indicate that this works okay so far.

One question i have is; Why has the MegaWizard configured my custom ALT2GXB MegaFunction's single-wire outputs as 2-wire buses? For instance, see the 'rx_ctrldetect' signal in the attached JPG - i don't know whether to look at bit 0 or 1. For this signal, it seems logical to ignore bit 1 but for other signals both bits [1..0] toggle more frequently.

Edit: After learning some more, i now realize that the [1:0] status bits are such that status of both bytes in the rx_dataout[15:0] bus can be determined.