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Altera_Forum
Honored Contributor
16 years agoThe problem was in incorrect interpretation of 64 bit interface. We thought that this interface like XGMII after DDR registers - lanes 0,1,2,3 are on rising (falling) edge and lanes 4,5,6,7 are on falling (rising) edge. We were just confused :) In reality it has another order (RTFM):lanes 0,2,4,6 at clock N and lanes 1,3,5,7 at clock N+1.
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