Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi,
As you discovered: changing the MIF is not changing the actual pll. I used ECO changes to do this: 1) compile design once 2) go to chip planner and go to the pll: then change the pll settings 3) open the cange manager window (menu-->view --> utility windows) and commit changes Note: you can export your changes to a tcl script (in the change manager window rigth click) Suucess!