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Altera_Forum's avatar
Altera_Forum
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12 years ago

AHDL equivalent to Preserve in in Verilog

Hi I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out. I know that in Verilog, Prese...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

perhaps Tricky, you are right. but if you look better in code you find that there are 2 edges of clock instead of 1.

I don't like such bad time shifting that decrease setup times for outputs.

Then i suggest one (AlanIsmail) should open MAxPlus help file and read carefully about coding style for AHDL.