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Altera_Forum
Honored Contributor
Honored ContributorAHDL equivalent to Preserve in in Verilog
Hi I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out. I know that in Verilog, Prese...
Altera_ForumHonored Contributor
Honored ContributorThere is no requirement for a reset in a state machine. An initial value is good enough.
