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Altera_Forum
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12 years ago

AHDL equivalent to Preserve in in Verilog

Hi I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out. I know that in Verilog, Prese...
Altera_Forum's avatar
Altera_Forum
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10 years ago

or you can use Assignment Editor after Analysis and Elaboration stage. open assignment editor in Assignments menu look for you node in Node Finder in field TO (generally) make assignment for register or if it is really state-machine you can assign type of state-bits encoding