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Altera_Forum
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12 years ago

AHDL equivalent to Preserve in in Verilog

Hi I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out. I know that in Verilog, Prese...
Altera_Forum's avatar
Altera_Forum
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10 years ago

it cannot be fuly defined state-machine . you must provide 'reset' signal

also there are rules how to write code so synthesis tool aware state-machine.

you can make statemachine through TRUTH_TABLE in AHDL. it is only one operator that missed in VHDL.