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Altera_Forum
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12 years ago

AHDL equivalent to Preserve in in Verilog

Hi I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out. I know that in Verilog, Prese...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Figured out from *.vqm file that these nodes were renamed by quatus when logic packing happens ( ie combining com & registered function ) in a single LE.

for "s2_base_2" , the new name is s2_base_2~20 ( for registered output )

Can anybody help with tcl command to preserve the node coz it will help me .

Thanks