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Altera_Forum
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12 years ago

AHDL equivalent to Preserve in in Verilog

Hi I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out. I know that in Verilog, Prese...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The Quartus software manual tells about HDL synthesis directives

--- Quote Start ---

The AHDL language does not support the synthesis directives or attributes described in this chapter.

--- Quote End ---

Sounds like tcl commands respectively settings in the Quartus assignment editor are the only means to achieve what you want.