AHDL equivalent to Preserve in in Verilog

Hi

Below is the piece of SM in AHDL

base_2 :MACHINE WITH STATES (s0_ base_2,

s1_ base_2,

s2_ base_2,

s3_ base_2);

int_ff2.clk = h1;

int_ff2.d = zoom_a;

base_2.clk = !h1;

CASE ( base_2) IS

WHEN s0_ base_2 => /int2 = vcc;

IF int_ff2.q THEN base_2 = s1_ base_2;

ELSE base_2 = s0_ base_2;

END IF;

WHEN s1_ base_2 => /int2 = gnd;

base_2 = s2_ base_2;

WHEN s2_ base_2 => /int2 = gnd;

base_2 = s3_ base_2;

WHEN s3_ base_2 => /int2 = vcc;

IF int_ff2.q THEN base_2 = s3_ base_2;

ELSE base_2 = s0_ base_2;

END IF;

END CASE;

In Quartus simulation, I could not locate "s2_ base_2" , the warning message was

Warning: Can't display state machine states -- register holding state machine bit "s2_base_2" was synthesized away