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GS65's avatar
GS65
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3 years ago
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Agilex PCIe IP Bypass mode

I am trying to use the PCIe Hard IP in bypass mode. I would like to know the following. 1. Does the enable PCIe receive queues (P,NP,C) in bypass modes and handle flow control? 2. If so, is PCIe ...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi,

    Your understanding is correct, is there anything else you not understand and I can clarified more ?

    Regards,

    Wincent_Intel

GS65's avatar
GS65
Icon for New Contributor rankNew Contributor
3 years ago

Hi,

Thanks for the clarification. The following comment from you is not clear

>> "it is important to note that the PCIe specification requires strict ordering between posted TLPs and completion TLPs. In contrast, non-posted TLPs, such as NP and C TLPs, do not have such strict ordering requirements. This means that the IP may require separate flow control credits for different TLP types to ensure that the ordering requirements are met for posted TLPs, while allowing for more flexibility in the ordering of NP and C TLPs."

I am implementing relaxed ordering. With RO, non-posted (NP) and completion (C) TLPs cannot pass posted TLPs. So, if a posted TLP is next selected TLP as per RO rules, and the application has no posted credits the output should be blocked. In other words, posted TLPs cannot be bypassed even if I have credits for NP or C TLPs in the application. I agree that separate credits for NP and C TLPs may help in reordering those TLPs.

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Your understanding is correct, is there anything else you not understand and I can clarified more ?

Regards,

Wincent_Intel

  • GS65's avatar
    GS65
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi

    Thanks for the prompt replies. The functionality is pretty clear now.

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi,

      Glad that I am answering your question.

      Hence, This thread will be transitioned to community support.

      If you have a new question, feel free to open a new thread to get support from Intel experts.

      Otherwise, the community users will continue to help you on this thread. Thank you

      If you feel your support experience was less than a 9 or 10,

      please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

      Regards,

      Wincent_Intel

  • GS65's avatar
    GS65
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Vincent,

    I have a related question on AGF014 part. We are trying to build a PCIe switch with a AGF014 development board. (We ordered the DEV-AGF027 but there are supply issues with the board). We were under the impression that any of the 4 x4 ports in the P-tile can be configured as UPSTREAM or DOWNSTREAM ports. However we just found out that the tool only allows all x4's to be either UP or DN. As you can imagine we cannot build a switch will all UP or DN ports. Can we configure each of the 4 x4's in a P-tile to either UP or DN?

    Thanks

    GS

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