Forum Discussion
New ContributorAgilex PCIe IP Bypass mode
Hi,
Your understanding is correct, is there anything else you not understand and I can clarified more ?
Regards,Wincent_Intel
New ContributorHi,
Thanks for the quick reply.
I am referring to F-Tile Avalon® Streaming Intel®
FPGA IP for PCI Express* User Guide Updated for Intel® Quartus® Prime Design Suite: 22.4
IP Version: 8.0.0.
Section 3.3.2.1 says that RX flow control interface is optional and disabled by default in the IP GUI. Does the IP expect the application to maintain separate queues for data and headers for P,NP and C TLPs?
Is there a single flow control interface? If Relaxed ordering is implemented, NP and C TLPs cannot pass posted TLPs. So, why is the IP expecting separate flow control credits for the TLP types?
Thanks
Regular ContributorHi,
Does the IP expect the application to maintain separate queues for data and headers for P,NP and C TLPs?
>>The RX flow control interface is optional and disabled by default, meaning that the IP does not require the application to provide flow control credits for incoming TLPs.
Is there a single flow control interface?
>> if the RX flow control interface is optional and disabled by default, it suggests that the IP does not provide a dedicated flow control interface for each TLP type.
If Relaxed ordering is implemented, NP and C TLPs cannot pass posted TLPs. So, why is the IP expecting separate flow control credits for the TLP types?
>> it is important to note that the PCIe specification requires strict ordering between posted TLPs and completion TLPs. In contrast, non-posted TLPs, such as NP and C TLPs, do not have such strict ordering requirements. This means that the IP may require separate flow control credits for different TLP types to ensure that the ordering requirements are met for posted TLPs, while allowing for more flexibility in the ordering of NP and C TLPs.
Let me know if this answer your question or you need any further clarification.
Regards,
Wincent_Intel
- GS65
Hi,
Thanks for the clarification. The following comment from you is not clear
>> "it is important to note that the PCIe specification requires strict ordering between posted TLPs and completion TLPs. In contrast, non-posted TLPs, such as NP and C TLPs, do not have such strict ordering requirements. This means that the IP may require separate flow control credits for different TLP types to ensure that the ordering requirements are met for posted TLPs, while allowing for more flexibility in the ordering of NP and C TLPs."
I am implementing relaxed ordering. With RO, non-posted (NP) and completion (C) TLPs cannot pass posted TLPs. So, if a posted TLP is next selected TLP as per RO rules, and the application has no posted credits the output should be blocked. In other words, posted TLPs cannot be bypassed even if I have credits for NP or C TLPs in the application. I agree that separate credits for NP and C TLPs may help in reordering those TLPs.
- Wincent_Altera
Hi,
Your understanding is correct, is there anything else you not understand and I can clarified more ?
Regards,Wincent_Intel
- GS65
Hi Vincent,
I have a related question on AGF014 part. We are trying to build a PCIe switch with a AGF014 development board. (We ordered the DEV-AGF027 but there are supply issues with the board). We were under the impression that any of the 4 x4 ports in the P-tile can be configured as UPSTREAM or DOWNSTREAM ports. However we just found out that the tool only allows all x4's to be either UP or DN. As you can imagine we cannot build a switch will all UP or DN ports. Can we configure each of the 4 x4's in a P-tile to either UP or DN?
Thanks
GS
