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jmcguire3's avatar
jmcguire3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Agilex F-Tile tx_ready fails to assert

I'm starting a new thread, because the previous discussion was booted into the void: https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/Agilex-Ftile-is-not-asserting-tx-ready-after-the-reset-seq...
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Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


it's good to hear that your tx_ready asserts now. Are you toggling the reset line on the reconfiguration controller as part of post-device configuration. If not, toggle once.


Thank you,

Kshitij Goel


jmcguire3's avatar
jmcguire3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

The design I uploaded has the F-Tile reset signal sourced from (init_done || 1v2reset). 1v2reset is connected to GPIO Pin AB53 (FPGA_RESETn on the schematic, page 16) that's routed through the MAX10 to SYS_PB1 on the EVM.

Pressing-and-holding the SYS_PB1 button initiates and maintains the reset. The FGT outputs enter a "hard low" where both signals of the diff pair are down near ground.

Releasing the SYS_PB1 button returns the FGT outputs to a differential-zero - the (p) signals are above ground by about 100mV, and the (n) signals are up around 350mV. It's definitely a distinct change from the in-reset state, but the FGT outputs are stuck at all-zeroes.