Agilex DDR4 Interface Debug

Hi Emrah,

"EMIF Toolkit does not support Agilex Family FPGAs but EMIF IP user guide still address this toolkit for JTAG debugging."

Which EMIF Toolkit that you mean here?

"Is there a suggested methodology and/or tool for debugging DDR4 interfaces through JTAG? "

You can debug the EMIF interface with EMIF Debug Toolkit or On Chip Debug Port. The details can be referred to links below:

• https://www.intel.com/content/www/us/en/docs/programmable/683216/22-4-2-6-1/debugging-with-the-external-memory-interface.html
• https://www.intel.com/content/www/us/en/docs/programmable/683216/22-4-2-6-1/emif-on-chip-debug-port.html

"Can we debug HPS DDR4 using the same methodology?"

To debug the HPS EMIF, we will use Fabric EMIF IP with HPS EMIF pin placement. The HPS EMIF is not supported by the debugging tools.

Regards,

Adzim