Forum Discussion
Occasional ContributorAgilex 7 interface with DDR4
Super ContributorLike I said, you need to create an example design without the HPS and establish that your EMIF works. That warning means you are still trying to create the example design from the HPS EMIF IP, not the standalone EMIF IP.
But yes since it's just a warning, it's not an issue for now.
Occasional ContributorHi sstrell,
OK.
I recreate again based on the attached document.
By the way. I asked the hardware engineer, he told me their design is based on Intel Agilex 7 FPGA F-series transceiver-SoC Development kit.
Does that ring any bell to you?
Regards,
- sstrell
"Based on" or "is" an Agilex 7 F-series dev kit? If it actually is a dev kit, the GSRD is here and you can use that: https://www.rocketboards.org/foswiki/Documentation/AgilexSoCGSRD?erpm_id=7513446_ts1709705124515. If not, then you should continue getting the EMIF to work before incorporating the HPS.
- nelky
Hi sstrell,
I have created the stand-alone EMIF based on the ug-ag-emideug-683162-773463.pdf document up to the modelsim part. What to see if it is working?
I attach the screenshot of the modelsim here.
Regards,
- nelky
Hi sstrell,
In the document "ug-ag-emideug-683162-773463.pdf", I am stuck at
2.11. Using the Design Example with the EMIF Debug Toolkit
5. Click Open Toolkit to open the main view of the EMIF Debug Toolkit.
I can't see any button by the name "Open Toolkit"
I loaded my ed_synth.sof by clicking on "Load Design" button. Then my System Console is empty, as shown below,...
We need this to check if EMIF is working before incorporating the HPS, right?
Regards
