Forum Discussion
Occasional ContributorAgilex 7 interface with DDR4
Occasional ContributorIt fails with this error message when I tried to generate
HPS_OSC_CLK input is required to drive the main PLL. But the pin has not been specified in the HPS I/O selection.
Sorry, it's actually a warning. It matters also, right?
I am using Quartus Prime Pro 22.1.0 Build 174 03/03/2022 SC Pro Edition.
Platform Designer 22.1 Build 174.
Do you want me to PM you my Quartus projects?
Super ContributorLike I said, you need to create an example design without the HPS and establish that your EMIF works. That warning means you are still trying to create the example design from the HPS EMIF IP, not the standalone EMIF IP.
But yes since it's just a warning, it's not an issue for now.
- nelky
Hi sstrell,
OK.
I recreate again based on the attached document.
By the way. I asked the hardware engineer, he told me their design is based on Intel Agilex 7 FPGA F-series transceiver-SoC Development kit.
Does that ring any bell to you?
Regards,
- sstrell
"Based on" or "is" an Agilex 7 F-series dev kit? If it actually is a dev kit, the GSRD is here and you can use that: https://www.rocketboards.org/foswiki/Documentation/AgilexSoCGSRD?erpm_id=7513446_ts1709705124515. If not, then you should continue getting the EMIF to work before incorporating the HPS.
- nelky
Hi sstrell,
I have created the stand-alone EMIF based on the ug-ag-emideug-683162-773463.pdf document up to the modelsim part. What to see if it is working?
I attach the screenshot of the modelsim here.
Regards,
