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davidhorowitz
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5 months ago

Agilex 7 FP32/FP16 TFlops performance calculation

Hello, I would like to calculate the following metrics for the Agilex 7 series: -Peak FP32/FP16 FMA TFlops -Peak FP32/FP16 TFlops -Peak FP32/FP16 TFlops / mm^2 of fabric How would I calculate...
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Fpga Devkit
davidhorowitz's avatar
davidhorowitz
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5 months ago

For DDR4 memory, i have this equation:

DDR4 Memory Bandwidth = (Data Rate (MT/s) * Bus Width (bits) * #channels ) /8

Based on the F-Series product table I calculated the DDR4 memory bandwidth as follows:

DDR4 Memory Bandwidth = (3.2) * 64 * 4) / 8 = 102.4 GB/s

Does this make sense?

For the M20K and MLAB, I don't know what formula would be use to calculate bandwidth.