Forum Discussion
vika
New Contributor
1 year agoAgilex 7 E-tile Eye diagram viewer failure
Hi, I'm using a development board with an Intel Agilex AGFB014R24A2E2V. The FPGA E-tile transceivers are connected to 2 x QSFP28 cages to run 100G Ethernet. We now have the system up and running u...
vika
New Contributor
1 year agoHi Ash,
Thanks for your feedback!
I took some time to try using the E-Tile Transceiver PHY IP instead of the E-Tile Hard IP for Ethernet that I have used previously. I enabled the parameters you mentioned: Enable Dynamic Reconfiguration, Enable control and status registers, Enable capability registers.
I get the same result with the E-Tile Transceiver PHY IP: Failed to show eye data: index 0 out of bounds for length 0
I attach one screenshot for each scenario for you reference.
Best Regards
Viktor
With E-Tile Transceiver PHY IPWith E-Tile Hard IP for Ethernet