Forum Discussion
vika
New Contributor
New ContributorAgilex 7 E-tile Eye diagram viewer failure
Hi, I'm using a development board with an Intel Agilex AGFB014R24A2E2V. The FPGA E-tile transceivers are connected to 2 x QSFP28 cages to run 100G Ethernet. We now have the system up and running u...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
Q1) Have you enabled following parameters in the IP?
Enable Dynamic Reconfiguration
Enable Native PHY Debug Master Endpoint(NPDME)
Enable control and status registers
Enable capability registers
Q2) Once you make sure above settings are enabled, did you select the correct JTAG master in the system console?
Regards
vikaNew Contributor
New ContributorHi Ash!
Thank you for the reply!
It seems you are suggesting that we use the E-Tile CPRI PHY Intel FPGA IP to run the Eye diagram viewer?
Currently we are using the E-Tile Ethernet IP for Intel Agilex 7 FPGA, and it seems only part of the settings you are referring to are available among the parameters for this IP (I only find the setting "Enable Native PHY Debug Master Endpoint" which is enabled).
Best Regards,
Viktor
