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Altera_Forum's avatar
Altera_Forum
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12 years ago

Address alignment problem with Tristate Controller

Hi all,

I have a Generic Tristate Controller and a custom Tristate Controller interfacing two external devices via Tristate Pin Sharer. Both external devices have a 16bit data bus, therefore address[0] pin from Pin Sharer is not externally used, so in my top-level file I use: 

flash_lan_addr <= flash_lan_addr_local(flash_lan_addr_local'high DOWNTO (flash_lan_addr_local'low +1));

This worked fine while having two Gerneric Tristate Controllers, but with my custom Controller, I get a pointless error during Partition Merge:

--- Quote Start ---

Error (35030): Partition "fpga_sopc:U_1" contains I/O cells that do not connect to top-level pins or have illegal connectivity

Error (35032): Output port "fpga_sopc:U_1|tristate_bridge_tristate_bridge_address[0]" on partition "fpga_sopc:U_1" must drive a top-level pin but is driving "<nothing>"

--- Quote End ---

Of corse address[0] is driving nothing, there is nothing to drive!

I need help, what's the problem here?

My TCM Interface looks as follows: 

      tcm_data_in          : IN     std_logic_vector (15 DOWNTO 0);
      tcm_grant            : IN     std_logic;
      tcm_address_out      : OUT    std_logic_vector (7 DOWNTO 0);  -- Byte Address, Bit 0 is not used
      tcm_chipselect_n_out : OUT    std_logic;
      tcm_data_out         : OUT    std_logic_vector (15 DOWNTO 0);
      tcm_data_outen       : OUT    std_logic;
      tcm_read_n_out       : OUT    std_logic;
      tcm_request          : OUT    std_logic;
      tcm_reset_n_out      : OUT    std_logic;
      tcm_write_n_out      : OUT    std_logic

Thanks

Simon

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Scanning the report, I found these additional messages:

    --- Quote Start ---

    Info (35026): Attempting to remove 2 I/O cell(s) that do not connect to top-level pins or have illegal connectivity

    Info (35028): Failed to remove I/O cell "fpga_sopc:U_1|tristate_bridge_tristate_bridge_address[0]~output"

    Info (35027): Removed I/O cell "eth_top:U_10|tcm_address_out[0]~output"

    Critical Warning (35033): Found I/O pins in lower-level partitions that are not connected in the top-level design

    Critical Warning (35034): I/O cell "fpga_sopc:U_1|tristate_bridge_tristate_bridge_address[0]~output" is not connected to partition "fpga_sopc:U_1"

    --- Quote End ---

    This seems, like the Synthesizer recognized my custom TCM not using address[0] and therefore removing it, while failed to remove address[0] from the generic TCM (for whatever reason). Maybe this divergence causes the problem...

    I managed to get around this problem, by connecting address[0] to a spare pin... but honestly, this is no real solution :mad:
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    I found the problem myself:

    I had the setting "Ignore partition assignments during compilation" off, while my custom TC was in a different partition as the gerneric TC. Therefore optimization of address[0] failed :rolleyes:.

    Simon