ADC0848 interface with MAX EPM7128S

I know that You will be converting Analog signals into the digital domain: I guess this is why You are using the ADC!!!

My question was trying to understand more design specific requirements like:

1. what is going to be Your sampling rate;

2. Is the EPM going to be connected to an other device (processor or other CPLD)?

3. Are You going to process the digital samples within the EPM or are You going to use it only as a controller for the ADC?

The concer that I have is, that after revieweing the Datasheet, I am afraid that You will be seriously limited by the CPLD resources in being able to istanciate a State Machine which will cover all the possible operating conditions of the ADC.

This is the reason for my questions in the previous message and in this one.

In any case, a Finite State Machine is the best approach for controlling the ADC; there are samples on the ALTERA web sites and there is a lots of documentation that shows You how to make a FSM in VHDL. My recommendation is that You take those as samples and built the controller in the EPM initially with limited capabilities and improve it to verify that the design will fit in the EPM7128.

Regards