ADC Timing Constraints

Nope, test design doesn't work. I tried the following VHDL file as the entirety of the design logic:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity temp is
	port (
		CLK_125_IN   : in std_logic;
		ADC_DATA     : in std_logic_vector(7 downto 0);
		ADC_CLK      : out std_logic;
		LATCHED_DATA : out std_logic_vector(7 downto 0)
	);
end entity temp;
architecture Behavioral of temp is
begin
	
	process (CLK_125_IN)
		variable tff : boolean;
	begin
		if rising_edge(CLK_125_IN) then
			if tff then
				LATCHED_DATA <= ADC_DATA;
				ADC_CLK <= '1';
			else
				ADC_CLK <= '0';
			end if;
			
			tff := not tff;
		end if;
	end process;
end architecture Behavioral;

set_time_format -unit ns -decimal_places 3
create_clock -name {CLK125} -period 8.000 
create_generated_clock -name {tff_clk} -source  -divide_by 2  
create_generated_clock -name {adc_clk} -source   
set_input_delay -add_delay -rise -max -clock   12.000 ]
set_input_delay -add_delay -rise -min -clock   3.900 ]
set_multicycle_path -setup -end -from    -to   2
set_multicycle_path -hold  -end -from    -to   1