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Altera_Forum
Honored Contributor
Honored ContributorADC interfacing code for 3-wire SPI using Verilog
Hi guys, I'm writing some Verilog code to interface a simple 12-bit serial ADC to an FPGA and I have some questions about my methodology. The ADC that I'm using is the ADS7818 from Texas Ins...
Altera_ForumHonored Contributor
Honored ContributorThanks very much for the suggestions guys. I'm driving the clock through a PLL. The only way I was able to get a clock of that speed was through the PLL, first by generating a 32 MHz clock and then dividing it by 4 to get 8 MHz. For the added delays, is the only way to test than through actual experimentation? I'll have a go at it tomorrow to see how it fares.
