Forum Discussion
Occasional ContributorAccessing user data in configuration flash
Here is the solution - Instantiate the "Intel® FPGA Serial Flash Loader IP Core" and hook up a QSPI controller to this core.
Here is a link to YOUR document - 1.9. Intel® FPGA Serial Flash Loader IP Core Signals
Occasional ContributorWhen we try to assign the pins in the Pin Planner, it gives an error message that the pins are “not assignable”. When we do it manually in the Assignment Editor window and in the QSF file, but when we try to compile after that, it fails on the Fitter saying it “cannot place the components due to conflicts with existing constraints”.
We searched the issue online, and there was an Intel support page saying the pins not being assignable in user mode is an issue with Quartus, and to add two lines to the QSF file. we added those lines, but it gave usthe same issue when trying to compile. (Here’s the link to that page: How do I assign dual-purpose pins to be a user I/O after... (intel.com))
If there’s anything else you think we should try, let us know.
FvMSuper Contributor
You are linking a support page that is more than 10 years old referring to outdated Quartus versions.
Unfortunately we don't know your exact configuration and can't reproduce the issue. Can you archive a minimal design that demonstrates the problem?
