Forum Discussion
Occasional ContributorAccessing user data in configuration flash
Here is the solution - Instantiate the "Intel® FPGA Serial Flash Loader IP Core" and hook up a QSPI controller to this core.
Here is a link to YOUR document - 1.9. Intel® FPGA Serial Flash Loader IP Core Signals
Regular ContributorHi pgigliotti,
I wish to follow up with you about this case. Do you have any further questions on this matter? Otherwise, this thread will be idling and marked as inactive, thus it will be transitioned to community support because there is no update received from you in a while.
Regards,
Fakhrul
pgigliotti_uascI hope to have an answer later today, as to the viability of this solution.
- pgigliotti_uasc
When we try to assign the pins in the Pin Planner, it gives an error message that the pins are “not assignable”. When we do it manually in the Assignment Editor window and in the QSF file, but when we try to compile after that, it fails on the Fitter saying it “cannot place the components due to conflicts with existing constraints”.
We searched the issue online, and there was an Intel support page saying the pins not being assignable in user mode is an issue with Quartus, and to add two lines to the QSF file. we added those lines, but it gave usthe same issue when trying to compile. (Here’s the link to that page: How do I assign dual-purpose pins to be a user I/O after... (intel.com))
If there’s anything else you think we should try, let us know.
