Accessing JTAG_UART from Matlab

Hi Frank,

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The JTAG port is surely limited. I can't follow however the "polling" point as a serious argument against JTAG UART usability. Altera JTAG is polling the UART usually with 6 MBPS. So what? A FTDI chip is polled through USB with 12 MBPS. O.K., there's a kind of bottleneck in the JTAG protocol itself and VJTAG on top of it.

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I'll clarify this point, since there is polling done by the USB interface (to get data that is ready at the device) and there is polling at the application layer (performed by SystemConsole).

Polling done by the USB layer is just how USB works, so we can consider that 'for free', whereas polling by SystemConsole makes the interface less than ideal for use as a high-performance communications interface.

(Frank - I know you know most of the following, I'm just explaining the details for other readers of this post ...)

The USB-Blaster is implemented using an FTDI FT245 and a CPLD. The FT245 is operated in FIFO mode, where USB bytes are presented in parallel to the CPLD. Logic in the CPLD then interprets the bytes according to the protocol on the UrJTAG web site, and initiates JTAG serial activity. JTAG writes are always reads. A bit in one of the USB command bytes indicates whether the serial bits read by the CPLD should be packed into bytes and sent back over USB.

If you interface an FT245 directly to an FPGA in FIFO mode, you can stream bytes to/from the host computer at about 1MB/s. In this mode, the fpga can initiate data transfer to the host, by writing a byte directly to the FT245 FIFO interface. That byte gets sent over USB (USB polling collects it from the device) into the USB serial driver layer, and eventually your application 'read' call succeeds.

Using the USB-Blaster, to read bytes from your hardware, the host needs to send a stream of write (host-to-USB-Blaster) bytes, which are read by the USB-Blaster CPLD serialized to the JTAG interface on the FPGA. The TDO serial stream from from the FPGA is packed into bytes, and then sent back over JTAG. Because there is a CPLD between the FT245 and the FPGA, and the FPGA has no way of initiating data transfer to the host. The host has to poll the fpga jtag internal logic for data that the FPGA logic would like to send to the host.

The key difference for FPGA initiated transfers between these two cases, is for the FT245, the byte is sent directly when it is ready, and for the USB-Blaster, a host-to-FPGA data stream is needed to poll for that byte, the data stream has to be sent repeatedly until the byte is determined to be ready.

Arguably both cases are ultimately limited by the polled nature of USB. However, the direct connection between the FT245 and USB is a cleaner and higher-performance interface.

Cheers,

Dave