AC coupled LVDS input internal DC bias for Cyclone V

Indeed, the 1.25Vcm voltage is the DC bias operating point of the LVDS buffer input stage which is not intended to "provide' any voltage to its outside world.

Nevertheless, this is the voltage you will measure if you apply a voltmeter between GND and the input pins (p or n) as you've done and on every LVDS inputs.

Consequently, you cannot apply any DC voltage at this input otherwise you will change the circuit operating point (hence, the buffer performance or functionality).

If you implement DC coupling, your incoming signal shall not exceed the specified Vicm range.

If you implement AC coupling, you don't have to care about that 'cause the blocking capacitor will prevent the output LVDS driver from disturbing the receiver input stage bias point

It's the way it works for LVDS but for other differential logic standards with different Vcm as well (ECL, CML, ...).

Have a good design !