Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

AC coupled LVDS clock input - Stratix V

Hello, We are using one of the CLK inputs (not REFCLK) of our 5SGSMD5K2F40I2LN device as an LVDS receiver of a 54MHz clock. Currently our clock is ac coupled to the input (as illustrated be...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

See Altera's "do lvds receivers in altera devices have on-chip dc-biasing resistors? (do lvds receivers in altera devices have on-chip dc-biasing resistors?)" support solution. It confirms there are no biasing resistors inside the devices.

Perhaps also look at TI's "ac-coupling between differential lvpecl, lvds, hstl and cml (https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahukewjc5spj88flahvlcj4khatfaowqfggcmaa&url=http%3a%2f%2fwww.ti.com%2fcn%2flit%2fpdf%2fscaa059&usg=afqjcnfvvvaqdq2md_2ebflend_y9puhlw&bvm=bv.117218890,d.bgs)". This covers your case and suggests some biasing solutions.

Cheers,

Alex