About the Quartus II TimeQuest Timing Analyzer

A device bus output of the data clock of the D flip-flop 80M, B device with the clock of the D flip-flop of the same 80M to receive in my design. The two 80M clocks is from a clock chip fan out.A device sent out data read by signaltap file is correct, but the the B device receives data errors.I add A device output 2ns delay ,as well as add 2ns delay to the input of the device B, but it still errors.Therefore, I would like to know the impact of the delay on the data is what the timing analyzer, who can draw me a diagram to express the data and clock with the delay, the time of the output from the D flip-flop Tco , how to ensure the set-up time and hold time?Thank you