about the CONF_DONE in the PS configuration

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currently, everything goes fine, except that when I send out all the configuration file in .hex format, the conf_done is still low...................

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What does the nSTATUS pin do?

If it goes low, it indicates that the configuration file is 'bad'. This can happen if your PS controller has a logical error, or if there are reflections on the DCLK signal that cause the FPGA to be double clocked.

Have you checked with JTAG that the FPGA can be programmed correctly. Does the CONF_DONE signal assert?

Is this a BGA package, or a TQFP? Can you probe the pins directly?

Cheers,

Dave

Dear Dave, thanks, your document is very detailed, but I still cannot find out the answer to my problem, currently, everything goes fine, except that when I send out all the configuration file in .hex format, the conf_done is still low...................

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Man, nobody ever reads my documents .... :)

Yes, I use .rbf files; see p29, and p63.

Cheers,

Dave

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Thanks again, Dave, did you ever try to configure FPGA using .rbf or .hex file ?

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Man, nobody ever reads my documents .... :)

Yes, I use .rbf files; see p29, and p63.

Cheers,

Dave

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Thanks, Dave. There is said to be a low-to-high transition for the CONF_DONE in the end of the configuration, I just want to know, how does the Cyclone device know the configuration is done ? that is, how does the Cyclone device know the exact time that the configuration file (.hex) is sent out?

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Look at page 4, Figure 1, it shows you the timing parameters.

Look at the logic analyzer trace on p60. It shows CONF_DONE going high right after the last DCLK.

The Cyclone device will do the same thing (if its working properly).

Cheers,

Dave

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Dear all, I am trying to configure the Cyclone III device using the Passive Serial mode. In the very beginning, I draw the nCONFIG low, and subsequently the Cyclone III draw the nSTATUS low....the question is: why CONF_DONE is always low from the very beginning? As to the configuration handbook, there should be a high-to-low transition for the CONF_DONE... why?

In addition, there is said to be a low-to-high transition for the CONF_DONE in the end of the configuration, I just want to know, how does the Cyclone device know the configuration is done ?

PS. MSEL is 0000, and the clock is 1M, and the file format is .hex.

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Look at the timing diagrams on page 4 in this document:

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

CONF_DONE is low at first power-on, since the FPGA has not been configured. Then the next time you configure it, CONF_DONE starts out high.

Cheers,

Dave