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Dear all, I am trying to configure the Cyclone III device using the Passive Serial mode. In the very beginning, I draw the nCONFIG low, and subsequently the Cyclone III draw the nSTATUS low....the question is: why CONF_DONE is always low from the very beginning? As to the configuration handbook, there should be a high-to-low transition for the CONF_DONE... why?
In addition, there is said to be a low-to-high transition for the CONF_DONE in the end of the configuration, I just want to know, how does the Cyclone device know the configuration is done ?
PS. MSEL is 0000, and the clock is 1M, and the file format is .hex.
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Look at the timing diagrams on page 4 in this document:
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf CONF_DONE is low at first power-on, since the FPGA has not been configured. Then the next time you configure it, CONF_DONE starts out high.
Cheers,
Dave
Honored Contributor
