About the ALT_ASMI core

The FPGA connection to the EPCS device is through the pins reserved exclusively for this connection. If you are using active serial programming to load the FPGA, you already have this connection in place.

For Stratix II/III/IV devices, the core connection to the pins is implicit - it's never seen in the user design. The instantiation of the core causes the connection to be made. This happens automatically if you use sopc_builder and add a epcs_controller, too. Similar "magic" happens with instantiations of the remote update core, and presumably with the JTAG debug logic in NIOSII.

I expect that this "magic" does not allow for more than one instance of the ALT_ASMI core, and you probably cannot have an instance of the ALT_ASMI core in a design that uses the sopc_builder epcs_controller. But I'm speculating about that.

I think that Cyclone III devices may need explicit connections to the EPCS signals - look for a reference design that uses the EPCS. (Anyone remember which Cyclone III boards have EPCS?)

\chuck