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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

About pin states from the end of MAX10 configuration to transition to user mode

According to the Intel® MAX® 10 FPGA Configuration User Guide, logic and registers are initialized and I/O buffers are enabled after configuration is complete. It would be helpful if you could teach ...
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NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
2 years ago

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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