Forum Discussion
Yamada1
Occasional Contributor
Occasional ContributorAbout pin states from the end of MAX10 configuration to transition to user mode
According to the Intel® MAX® 10 FPGA Configuration User Guide, logic and registers are initialized and I/O buffers are enabled after configuration is complete. It would be helpful if you could teach ...
NurAiman_M_Intel
Super Contributor
Super ContributorHi,
Any other information needed for this case? Else I will proceed to close this case for now.
Regards,
Aiman
