It would be helpful if you could tell us the following points about the rden signal input to the RAM block.
1) Reading is valid when rden is 'H', but is the read address latched even if rden is 'L'...
1) No, the read address do not latched when rden is L. It is this (addressstall = 1) signal that holds the previous address value for as long as the signal is enabled.
2) I don't get the meaning or the motivation behind the first sentence "In Figures 7 to 11 on page 41 of the user guide, q becomes Hi-Z at the rising edge of the next clock after rden becomes 'L'." I will answer the question for figure 4 instead - the question is a bit weird, it feel like asking two different things in one question... probably due to the translation I guess, but I will try to answer as best as possible.
dout0 is not the contents of read address a1, it is the contents from address a0. data N out from address N.
dout0 is the data that was read in the first clock cycle at address a0. So if rden become L at address a1, the q (synch) will still be dout0 at 2nd clock cycle as it was already read in the 1st clock cycle. But since the address a1 is not read in the 2nd clock cycle, the data at the next or 3rd clock cycle will retain as data dout0.
3) As explained in Q2, data would not be read if rden is low. If you create the read-enable port and perform a write operation (with the read enable port deasserted ), the data output port retains the previous values that are held during the most recent active read enable. Likewise, if you activate the read enable during a write operation, the output port shows the new data being written, the old data at that address, or a “Don't Care” value when read-during-write occurs at the same address location.
Best Regards,
Richard Tan
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p/s: Please do expert delay in response due to lunar new year.
I recognized that the read address is not latched when RDEN is 'L', and the data of the last latched address during the period when RDEN is 'H' is output at the next clock.
In the figure you posted, a0 is latched at 1st CLK and selection of dout0 is completed, so rden is 'L' at 2nd CLK, but q(synch) outputs dout0.
Is it correct to understand that q(synch) continues to output dout0 when rden is 'L' after the 3rd CLK?
We apologize for the inconvenience, but thank you in advance.
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