A10 SoC boot failure !

hi,

SoC Booting happening though SDcard with early IO release configuration.

Is there any limitation for the early IO release configuration as i am facing this issue after adding HIP pcie rootport along with EMIF and a HIP PCIe Endpoint.

can somebody please put some light on this topic!!

valuable suggestions are most welcome.

following is the log .

........................................................................................................................................

U-Boot 2014.10-00328-g2a2102e-dirty (Sep 22 2017 - 13:32:45)

CPU : Altera SOCFPGA Arria 10 Platform

BOARD : Altera SOCFPGA Arria 10 Dev Kit

I2C: ready

DRAM: WARNING: Caches not enabled

SOCFPGA DWMMC: 0

FPGA: writing ghrd_10as066n2.periph.rbf ...

FPGA: Early Release Succeeded.

DDRCAL: Success

INFO : Skip relocation as SDRAM is non secure memory

Reserving 2048 Bytes for IRQ stack at: ffe386e8

DRAM : 1 GiB

WARNING: Caches not enabled

MMC: *** Warning - bad CRC, using default environment

In: serial

Out: serial

Err: serial

Model: SOCFPGA Arria10 Dev Kit

Skipped ethaddr assignment due to invalid EMAC address in EEPROM

Net: dwmac.ff800000

Error: dwmac.ff800000 address not set.

Hit any key to stop autoboot: 5 4 3 2 1 0

FPGA: writing ghrd_10as066n2.core.rbf ...

Full Configuration Succeeded.

** Unable to read file u-boot.scr **

4377664 bytes read in 204 ms (20.5 MiB/s)

26597 bytes read in 10 ms (2.5 MiB/s)

FPGA BRIDGES: enable

Fail: noc_idleack = 0x00110000 mask_noc = 0x01010111

Kernel image @ 0x008000 [ 0x000000 - 0x42cc40 ]

## Flattened Device Tree blob at 00000100

Booting using the fdt blob at 0x000100

Loading Device Tree to 01ff6000, end 01fff7e4 ... OK

Starting kernel ...