Forum Discussion
Deshi_Intel
Regular Contributor
6 years agoHi,
Sorry, the problem right now is on the silicon limitation where it's hard to close timing with RGMII interface interface with FPGA IO.
So, the issue is not about the conversion anymore but we simply can't support RGMII interface usage on Arria 10 FPGA IO pins.
This is silicon hardware limitation, not about IP core usage.
Regards,
dlim