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Altera_Forum's avatar
Altera_Forum
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18 years ago

A very basic newbie question

Hi All I have a very basic question. I've recently started learning about CPLD and VHDL. My VHDL code usually compiles and simulates fine, but when I put it in an actual CPLD it behaves really...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

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Thanks for all your answers, very informative. I have improved my code a lot.

All my problems went away (even using the original code) when I changed the policy for unused pins from "As output driving an unspecified signal" to "As input tri-stated ". Anyone knows why?

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The default setting of Quartus for unused pins ( Output driving ..) is dangerous in case of

FPGA boards with external components. It is very likely that unused FPGA outputs will drive against ouputs of other components.