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Altera_Forum's avatar
Altera_Forum
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17 years ago

a question about verilog hdl?

i have a question about this below: is there some differences betwen if (a == 0) and if (!a),I tried a number of simple examples, no difference. Do you think so?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

For the case you are looking at (a == 0) vs !a, it is likely the synthesis tool will optimize to the same thing in the end.

However, I have seen a performance increase when comparing two signals using

!(a ^ b)

vs.

(a == b)

The performance increase comes at the expense of using one more LUT.

Jake