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Altera_Forum's avatar
Altera_Forum
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14 years ago

A Question About Registers

Hello everybody!

I have a question;

In my design, i use verilog language and system works only when a command is recieved from the external controller and when the command is executed, goes back to wait state.

i have a "is in wait state?" control block and i initialize some registers with default values in this block.

Question is, when fpga is in wait state forever, these registers are set to the default values forever in the same loop and i wonder if this may harm the flip-flop regsters in the future or not. do i have to put an enable signal? or can i be sure that continuously setting a value to a flip-flop brings no problem?

thanks..

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    That will be no problem. An enable signal may help reduce power usage though, but for just a few registers, it wont make a noticable difference.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Usual FPGA families have no decidated enable signal for synchronous registers. In so far, using an enable signal doesn't keep the register from being "set to the default values forever". You would need a gated clock to save an additional (actually small) amount of power. More dynamical power is dissipated by toggling registers, however.